Workshop on Analog IC Design

Dates:   21 July 2012 – 25 July 2012

Course Overview

This is an introductory level course designed for engineers who are interested in learning about Analog Integrated Circuit (AIC) Design. The fundamental building blocks used in analog circuit are covered from a theoretical perspective as well as simulated using Electronic Design Automation (EDA) tools.

Who should attend?

This workshop assumes basic understanding of semiconductor devices, analog circuitry and EDA tool usage. If you are an Analog designer who plans to design analog circuits with a solid understanding of the underlying concepts then this is an ideal workshop for you. Moreover if you wish to get hands-on exposure in Synopsys Cdesigner, HSpice and WaveView then this workshop will provide a great opportunity to learn while getting a stronger understanding of analog design.

Trainer Profile

The training shall be conducted by Harutyun Stepanyan from Synopsys, Armenia.

Training Content

Day1 Morning (3-4 hours)

● Introduction to WaferCat’s Muli-Project Wafer (MPW) fabrication services

● Review of transistor operation

● Lecture classes

● MOS I/V characteristics: threshold voltage, derivation of I/V characteristics

● Transistor second order effects: body effect, channel length modulation, sub threshold conduction and voltage limitation

● Small signal model: transconductance and body effect transconductance, channel length impedance, capacitances of transistor

● Laboratory (hands on workshop) assignments

Day2 Morning (3-4 hours)

● Single stage amplifiers

● Lecture classes

● Gain of common-source stage amplifier using small signal analysis

● Common-source stage with resistive load, diode-connected load, current-source load, triode load, source degeneration

● Source follower stage

● Common-gate stage

● Cascode stages, folded cascode

● Laboratory (hands on workshop) assignments

Day3 Morning (3-4 hours)

● Differential amplifier

● Lecture classes

● Single-ended and differential operation

● Basic differential pair: qualitative analysis, quantitative analysis

● Common-mode response: CM noise, CMRR

● Differential pair with MOS loads: differential pair with diode connected and current source loads

● Layout issues and recommendations

● Laboratory (hands on workshop) assignments

Day4 Morning (3-4 hours)

● Current Mirrors

● Lecture classes

● Basic and cascode current mirrors

● Using active current mirrors as loads: active current mirrors, large-signal analysis, small-signal analysis, common-mode properties, CMRR calculating

● Layout issues and recommendations

● Laboratory (hands on workshop) assignments

Day5 Morning (3-4 hours)

● Overview of design/analysis available in Synopsys curriculum for the further development

● Introduction to slides, laboratory works and course project of Analog IC Design and other available courses which can be used for further development