WaferCatalyst, an initiative of King Abdulaziz City for Science and Technology (KACST), is pleased to announce post-graduate projects for 2014/15 in Integrated Circuit (IC) Design. Successful selected projects from this list may be eligible for WaferCatalyst Project Awards 2014-15 which includes FREE Fabrication of chips expected to be announced in July 2015.
1. Design of Sigma Delta Analog to Digital converter for high resolution, medium frequency audio or energy measurement applications
Audio and energy metering are examples of applications that require a high resolution but medium/low analog to digital conversion rate. One of the widely used architectures to achieve a high resolution at medium conversion rates is an oversampled Sigma Delta Analog to Digital converter (ADC).
In this technique a signal is modulated, sampled and then quantized (at low resolution) which introduces quantization error noise. The delta modulation encodes the change in signal which gives a stream of pulses as output. The signal is reproduced by passing the digital output through a 1-bit DAC and adding the analog signal to it. This reduces the error in the signal. Afterwards a digital filter is used to get a higher resolution but lower frequency signal. The major advantage of this design is that the analog circuits do not have to be very high resolution thus easing the design challenge in the analog domain.
The project involves the design of a high resolution (18-24 bits) that can work at moderate conversion rates (around 20kHz). This ADC design has elements of modeling, analog circuit design and digital IC design.
Recommended group: 2-3 students
2. Characterization and Implementation of Injection Locked Frequency Dividers of even and/or odd division ratios.
High-speed frequency dividers have vital role in today’s communication technology especially wireless communication technology. Systems like frequency synthesis and multiplexing (MUX/DEMUX) require high speed frequency dividers.
Digital frequency dividers are used usually up to few Giga Hertz frequency ranges, but frequency divider power consumption is going up with frequency. This can be a problem from two points of view, one is that it is not suitable for portable battery operated devices; the second is that having a high frequency switching activity generates high noise in present SOCs. This mandates a high frequency divider without such high power dissipation.
Injection Locked Frequency Divider (ILFD) has a big advantage over the digital frequency divider in terms of power dissipation for comparable speed performance. The common limitation of ILFD is the narrow frequency range.
The proposed research project is to design a “/2” and “/3” ILFD with input frequency about 10GHz and locking range around 1GHz for no more than 4dbm injected signal power and low power dissipation compared to current literature. The selection of dividing ratio should be programmable with a single bit.
Recommended group: 1-2 students
3. DC-DC converter for inertial sensor applications:
DC to DC converters are becoming very important in today’s portable computing and communication technologies. Battery operated electronic devices like laptops and cellular phone often use higher (or lower) than battery voltage for biasing and input/output (I/O) circuits. This necessitates the conversion of the battery’s DC voltage to another DC voltage. Usually DC-DC converter is regulated such that the change of output voltage with output current is very low.
The research proposes to design a high-efficiency DC-DC converter with programmable output voltage level. Using a CMOS technology with 1.8V core voltage and 3.3V I/O voltage, it is required to design a circuit that gives one of three outputs 1.8V, 5V and 7.5V selected by a 2-bit input control signal. The rationale for the 1.8V and 7.5V outputs is to be used in “reading from”/”writing to” a ROM, while the 5V output would be used in driving a block that needs a USB voltage level.
Recommended group: 2-3 students
4. Design of Wireless Battery-less Transceiver for Biomedical Applications
Battery-less circuit applications are becoming very important is a number of fields like commerce, security, military and medicine. Using batteries is not a feasible option in many applications (e.g. RFID monitoring devices) since it would make such applications hard to maintain, expensive and less reliable. Thus battery-less option is highly preferred in many cases.
The project envisions the design of a reliable battery-less implanted sensor/transmitter for the patients who need continuous monitoring for indicating parameters (e.g. pulse rate and blood characteristics like glucose level). These sensors are proposed to use MEMS technology and are to be attached with a transmitter for communicating sensor information and a unique ID for each patient.
The detailed specifications for the application under research should be determined according to the type of medical monitoring application that should carefully be selected through surveys of the latest medical research and/or in cooperation with a medical third party.
Recommended group: (2/3) – (3/4) students
5. Area/Energy-Efficient Hardware Design and Implementation of Digital Signal Processing Algorithms/Architectures used in Wireless Sensor Nodes
Wireless Sensor Network (WSN) has emerged as the preferred solution for a wide range of monitoring applications. Typically, a WSN comprises of autonomous sensor nodes that sense various phenomena. Each sensor node is composed of a limited number of components including: an analog front-end (sensor Interface), a processor, a radio transceiver and a power management circuit together with batteries. These sensor nodes then transmit their data continuously through a wireless connection to a master node, that collects, visualizes and analyzes the data.
The current challenge in WSN is the reduction of power consumption to reduce the dependency on batteries and allow miniaturization of the nodes. Reduction of power consumption can be done at the level of each component composing the sensor node, and the trade-off between local Digital Signal Processing (DSP) and radio transmission turns out to be very important. It has been shown that, with off-the-shelf radio such as Zigbee, it is always more attractive to process the data locally on the node, therefore reducing the amount of data to be transmitted, before sending it out through the radio link for reception by the master node.
The objective of this project is to develop embedded low power signal processing architectures for WSN. More specifically, the project will start from existing algorithms/architectures and will aim at optimizing them for real-time and energy efficient signal processing and implementation on chip. Several algorithms (FIR, FFT, Wavelet, Viterbi, etc.) will be considered which exhibit variable computational complexity. Parametrized VHDL/Verilog RTL codes corresponding to the selected algorithm/architecture will be developed. The developed architectures will be prototyped using low-power FPGAs before the actual tapeout of the chip. Performance evaluation can be done for both FPGA/ASIC and the results will be compared with the state-of-the-art.
Recommended Group: 1-2 students
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